diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/wiring/WiringTransform.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/wiring/WiringTransform.scala | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala index 20fb1215..d6658f16 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala @@ -14,14 +14,12 @@ import firrtl.stage.Forms case class WiringException(msg: String) extends PassException(msg) /** A component, e.g. register etc. Must be declared only once under the TopAnnotation */ -case class SourceAnnotation(target: ComponentName, pin: String) extends - SingleTargetAnnotation[ComponentName] { +case class SourceAnnotation(target: ComponentName, pin: String) extends SingleTargetAnnotation[ComponentName] { def duplicate(n: ComponentName) = this.copy(target = n) } /** A module, e.g. ExtModule etc., that should add the input pin */ -case class SinkAnnotation(target: Named, pin: String) extends - SingleTargetAnnotation[Named] { +case class SinkAnnotation(target: Named, pin: String) extends SingleTargetAnnotation[Named] { def duplicate(n: Named) = this.copy(target = n) } @@ -76,8 +74,9 @@ class WiringTransform extends Transform with DependencyAPIMigration { (sources.size, sinks.size) match { case (0, p) => state case (s, p) if (p > 0) => - val wis = sources.foldLeft(Seq[WiringInfo]()) { case (seq, (pin, source)) => - seq :+ WiringInfo(source, sinks(pin), pin) + val wis = sources.foldLeft(Seq[WiringInfo]()) { + case (seq, (pin, source)) => + seq :+ WiringInfo(source, sinks(pin), pin) } val annosx = state.annotations.filterNot(annos.toSet.contains) transforms(wis) |