1 files changed, 8 insertions, 10 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
index 943c71c7..7a6fcc65 100644
--- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
+++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala
@@ -63,19 +63,18 @@ class WiringTransform extends Transform with SimpleRun {
         ResolveKinds,
         ResolveGenders)
   def execute(state: CircuitState): CircuitState = getMyAnnotations(state) match {
-    case Some(p) => 
+    case Nil => CircuitState(state.circuit, state.form)
+    case p => 
       val sinks = mutable.HashMap[String, String]()
       val sources = mutable.Set[String]()
       val tops = mutable.Set[String]()
       val comp = mutable.Set[String]()
-      p.values.foreach { a =>
-        a match {
-          case SinkAnnotation(m, pin) => sinks(m.name) = pin
-          case SourceAnnotation(c) =>
-            sources += c.module.name
-            comp += c.name
-          case TopAnnotation(m) => tops += m.name
-        }
+      p.foreach { 
+        case SinkAnnotation(m, pin) => sinks(m.name) = pin
+        case SourceAnnotation(c) =>
+          sources += c.module.name
+          comp += c.name
+        case TopAnnotation(m) => tops += m.name
       }
       (sources.size, tops.size, sinks.size, comp.size) match {
         case (0, 0, p, 0) => state
@@ -84,6 +83,5 @@ class WiringTransform extends Transform with SimpleRun {
           state.copy(circuit = runPasses(state.circuit, passSeq(winfo)))
         case _ => error("Wrong number of sources, tops, or sinks!")
       }
-      case None => state
   }
 }