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-rw-r--r--src/main/scala/firrtl/passes/wiring/Wiring.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/Wiring.scala b/src/main/scala/firrtl/passes/wiring/Wiring.scala
index 45eb61bf..c5faefac 100644
--- a/src/main/scala/firrtl/passes/wiring/Wiring.scala
+++ b/src/main/scala/firrtl/passes/wiring/Wiring.scala
@@ -50,7 +50,7 @@ class Wiring(wiSeq: Seq[WiringInfo]) extends Pass {
portNames(i) = portNames(i) +
(m.name -> {
if (si.exists(getModuleName(_) == m.name)) ns.newName(p)
- else ns.newName(tokenize(c).filterNot("[]." contains _).mkString("_"))
+ else ns.newName(tokenize(c).filterNot("[]." `contains` _).mkString("_"))
})
}
}