diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemUtils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala index bb441ebb..69c6b284 100644 --- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala +++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala @@ -56,7 +56,7 @@ object MemPortUtils { type Modules = collection.mutable.ArrayBuffer[DefModule] def defaultPortSeq(mem: DefMemory): Seq[Field] = Seq( - Field("addr", Default, UIntType(IntWidth(ceilLog2(mem.depth) max 1))), + Field("addr", Default, UIntType(IntWidth(getUIntWidth(mem.depth - 1) max 1))), Field("en", Default, BoolType), Field("clk", Default, ClockType) ) |