diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib')
3 files changed, 24 insertions, 24 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index f524d60b..0602e4f1 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -8,7 +8,7 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.PrimOps._ import firrtl.Utils.{one, zero, BoolType} -import firrtl.options.HasScoptOptions +import firrtl.options.{HasShellOptions, ShellOption} import MemPortUtils.memPortField import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin} import WrappedExpression.weq @@ -147,17 +147,16 @@ object InferReadWritePass extends Pass { // Transform input: Middle Firrtl. Called after "HighFirrtlToMidleFirrtl" // To use this transform, circuit name should be annotated with its TransId. -class InferReadWrite extends Transform with SeqTransformBased with HasScoptOptions { +class InferReadWrite extends Transform with SeqTransformBased with HasShellOptions { def inputForm = MidForm def outputForm = MidForm - def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser - .opt[Unit]("infer-rw") - .abbr("firw") - .valueName ("<circuit>") - .action( (_, c) => Seq(InferReadWriteAnnotation, RunFirrtlTransformAnnotation(new InferReadWrite)) ++ c ) - .maxOccurs(1) - .text("Enable readwrite port inference for the target circuit") + val options = Seq( + new ShellOption[Unit]( + longOption = "infer-rw", + toAnnotationSeq = (_: Unit) => Seq(InferReadWriteAnnotation, RunFirrtlTransformAnnotation(new InferReadWrite)), + helpText = "Enable read/write port inference for memories", + shortOption = Some("firw") ) ) def transforms = Seq( InferReadWritePass, diff --git a/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala b/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala index 2f26e4e5..4076d5d6 100644 --- a/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala +++ b/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala @@ -3,13 +3,14 @@ package firrtl.passes.memlib import firrtl._ -import firrtl.options.RegisteredLibrary +import firrtl.options.{RegisteredLibrary, ShellOption} import scopt.OptionParser class MemLibOptions extends RegisteredLibrary { val name: String = "MemLib Options" - def addOptions(p: OptionParser[AnnotationSeq]): Unit = - Seq( new InferReadWrite, - new ReplSeqMem ) - .map(_.addOptions(p)) + + val options: Seq[ShellOption[_]] = Seq( new InferReadWrite, + new ReplSeqMem ) + .flatMap(_.options) + } diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala index 32d83181..a9d0cc7c 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala @@ -6,7 +6,7 @@ package memlib import firrtl._ import firrtl.ir._ import firrtl.annotations._ -import firrtl.options.HasScoptOptions +import firrtl.options.{HasShellOptions, ShellOption} import AnalysisUtils._ import Utils.error import java.io.{File, CharArrayWriter, PrintWriter} @@ -102,18 +102,18 @@ class SimpleTransform(p: Pass, form: CircuitForm) extends Transform { class SimpleMidTransform(p: Pass) extends SimpleTransform(p, MidForm) // SimpleRun instead of PassBased because of the arguments to passSeq -class ReplSeqMem extends Transform with HasScoptOptions { +class ReplSeqMem extends Transform with HasShellOptions { def inputForm = MidForm def outputForm = MidForm - def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser - .opt[String]("repl-seq-mem") - .abbr("frsq") - .valueName ("-c:<circuit>:-i:<filename>:-o:<filename>") - .action( (x, c) => Seq(passes.memlib.ReplSeqMemAnnotation.parse(x), - RunFirrtlTransformAnnotation(new ReplSeqMem)) ++ c ) - .maxOccurs(1) - .text("Replace sequential memories with blackboxes + configuration file") + val options = Seq( + new ShellOption[String]( + longOption = "repl-seq-mem", + toAnnotationSeq = (a: String) => Seq( passes.memlib.ReplSeqMemAnnotation.parse(a), + RunFirrtlTransformAnnotation(new ReplSeqMem) ), + helpText = "Blackbox and emit a configuration file for each sequential memory", + shortOption = Some("frsq"), + helpValueName = Some("-c:<circuit>:-i:<file>:-o:<file>") ) ) def transforms(inConfigFile: Option[YamlFileReader], outConfigFile: ConfWriter): Seq[Transform] = Seq(new SimpleMidTransform(Legalize), |