diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib')
4 files changed, 2 insertions, 9 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala index aa20e41e..412098fd 100644 --- a/src/main/scala/firrtl/passes/memlib/DecorateMems.scala +++ b/src/main/scala/firrtl/passes/memlib/DecorateMems.scala @@ -3,8 +3,6 @@ package firrtl package passes package memlib -import annotations._ -import wiring._ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform { def inputForm = MidForm @@ -14,10 +12,8 @@ class CreateMemoryAnnotations(reader: Option[YamlFileReader]) extends Transform case Some(r) => import CustomYAMLProtocol._ val configs = r.parse[Config] - val cN = CircuitName(state.circuit.main) val oldAnnos = state.annotations val (as, pins) = configs.foldLeft((oldAnnos, Seq.empty[String])) { case ((annos, pins), config) => - val source = SourceAnnotation(ComponentName(config.source.name, ModuleName(config.source.module, cN)), config.pin.name) (annos, pins :+ config.pin.name) } state.copy(annotations = PinAnnotation(pins.toSeq) +: as) diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 1663efaa..44f45985 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -85,8 +85,6 @@ object InferReadWritePass extends Pass { (s: Statement): Statement = s match { // infer readwrite ports only for non combinational memories case mem: DefMemory if mem.readLatency > 0 => - val ut = UnknownType - val ug = UNKNOWNGENDER val readers = new PortSet val writers = new PortSet val readwriters = collection.mutable.ArrayBuffer[String]() diff --git a/src/main/scala/firrtl/passes/memlib/MemIR.scala b/src/main/scala/firrtl/passes/memlib/MemIR.scala index aa60fca0..2379feab 100644 --- a/src/main/scala/firrtl/passes/memlib/MemIR.scala +++ b/src/main/scala/firrtl/passes/memlib/MemIR.scala @@ -3,7 +3,6 @@ package firrtl.passes package memlib -import firrtl._ import firrtl.ir._ object DefAnnotatedMemory { diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index f06ca61a..10bcadfb 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -41,7 +41,7 @@ object VerilogMemDelays extends Pass { if !ports(newName) } yield newName).head val rwMap = (sx.readwriters map (rw => - rw -> (newPortName(rw, "r"), newPortName(rw, "w")))).toMap + rw ->( (newPortName(rw, "r"), newPortName(rw, "w")) ))).toMap // 1. readwrite ports are split into read & write ports // 2. memories are transformed into combinational // because latency pipes are added for longer latencies @@ -59,7 +59,7 @@ object VerilogMemDelays extends Pass { // 2) pipe registers and connects val node = DefNode(NoInfo, namespace.newTemp, netlist(e)) val wref = WRef(node.name, e.tpe, NodeKind, MALE) - ((0 until n) foldLeft (wref, Seq[Statement](node))){case ((ex, stmts), i) => + ((0 until n) foldLeft( (wref, Seq[Statement](node)) )){case ((ex, stmts), i) => val name = namespace newName s"${LowerTypes.loweredName(e)}_pipe_$i" val exx = WRef(name, e.tpe, RegKind, ug) (exx, stmts ++ Seq(DefRegister(NoInfo, name, e.tpe, clk, zero, exx)) ++ |