diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib')
3 files changed, 47 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 2d1d7f6b..3494de45 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -8,10 +8,14 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.PrimOps._ import firrtl.Utils.{one, zero, BoolType} +import firrtl.options.HasScoptOptions import MemPortUtils.memPortField import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin} import WrappedExpression.weq import annotations._ +import scopt.OptionParser +import firrtl.stage.RunFirrtlTransformAnnotation + case object InferReadWriteAnnotation extends NoTargetAnnotation @@ -72,10 +76,10 @@ object InferReadWritePass extends Pass { def replaceStmt(repl: Netlist)(s: Statement): Statement = s map replaceStmt(repl) map replaceExp(repl) match { - case Connect(_, EmptyExpression, _) => EmptyStmt + case Connect(_, EmptyExpression, _) => EmptyStmt case sx => sx } - + def inferReadWriteStmt(connects: Connects, repl: Netlist, stmts: Statements) @@ -143,9 +147,18 @@ object InferReadWritePass extends Pass { // Transform input: Middle Firrtl. Called after "HighFirrtlToMidleFirrtl" // To use this transform, circuit name should be annotated with its TransId. -class InferReadWrite extends Transform with SeqTransformBased { +class InferReadWrite extends Transform with SeqTransformBased with HasScoptOptions { def inputForm = MidForm def outputForm = MidForm + + def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser + .opt[Unit]("infer-rw") + .abbr("firw") + .valueName ("<circuit>") + .action( (_, c) => c ++ Seq(InferReadWriteAnnotation, RunFirrtlTransformAnnotation(new InferReadWrite)) ) + .maxOccurs(1) + .text("Enable readwrite port inference for the target circuit") + def transforms = Seq( InferReadWritePass, CheckInitialization, diff --git a/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala b/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala new file mode 100644 index 00000000..2f26e4e5 --- /dev/null +++ b/src/main/scala/firrtl/passes/memlib/MemLibOptions.scala @@ -0,0 +1,15 @@ +// See LICENSE for license details. + +package firrtl.passes.memlib + +import firrtl._ +import firrtl.options.RegisteredLibrary +import scopt.OptionParser + +class MemLibOptions extends RegisteredLibrary { + val name: String = "MemLib Options" + def addOptions(p: OptionParser[AnnotationSeq]): Unit = + Seq( new InferReadWrite, + new ReplSeqMem ) + .map(_.addOptions(p)) +} diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala index 311813db..f2e6cd4e 100644 --- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala +++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala @@ -6,10 +6,13 @@ package memlib import firrtl._ import firrtl.ir._ import firrtl.annotations._ +import firrtl.options.HasScoptOptions import AnalysisUtils._ import Utils.error import java.io.{File, CharArrayWriter, PrintWriter} import wiring._ +import scopt.OptionParser +import firrtl.stage.RunFirrtlTransformAnnotation sealed trait PassOption case object InputConfigFileName extends PassOption @@ -19,11 +22,11 @@ case object PassModuleName extends PassOption object PassConfigUtil { type PassOptionMap = Map[PassOption, String] - + def getPassOptions(t: String, usage: String = "") = { // can't use space to delimit sub arguments (otherwise, Driver.scala will throw error) val passArgList = t.split(":").toList - + def nextPassOption(map: PassOptionMap, list: List[String]): PassOptionMap = { list match { case Nil => map @@ -103,9 +106,19 @@ class SimpleTransform(p: Pass, form: CircuitForm) extends Transform { class SimpleMidTransform(p: Pass) extends SimpleTransform(p, MidForm) // SimpleRun instead of PassBased because of the arguments to passSeq -class ReplSeqMem extends Transform { +class ReplSeqMem extends Transform with HasScoptOptions { def inputForm = MidForm def outputForm = MidForm + + def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser + .opt[String]("repl-seq-mem") + .abbr("frsq") + .valueName ("-c:<circuit>:-i:<filename>:-o:<filename>") + .action( (x, c) => c ++ Seq(passes.memlib.ReplSeqMemAnnotation.parse(x), + RunFirrtlTransformAnnotation(new ReplSeqMem)) ) + .maxOccurs(1) + .text("Replace sequential memories with blackboxes + configuration file") + def transforms(inConfigFile: Option[YamlFileReader], outConfigFile: ConfWriter): Seq[Transform] = Seq(new SimpleMidTransform(Legalize), new SimpleMidTransform(ToMemIR), |