diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala index 131a198b..dd644323 100644 --- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala @@ -175,7 +175,7 @@ object VerilogMemDelays extends Pass { Dependency[SystemVerilogEmitter] ) override def invalidates(a: Transform): Boolean = a match { - case _: transforms.ConstantPropagation => true + case _: transforms.ConstantPropagation | ResolveFlows => true case _ => false } |