diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemUtils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala index 709e57af..9328dfe4 100644 --- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala +++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala @@ -63,7 +63,7 @@ object MemPortUtils { ) // Todo: merge it with memToBundle - def memType(mem: DefMemory): Type = { + def memType(mem: DefMemory): BundleType = { val rType = BundleType(defaultPortSeq(mem) :+ Field("data", Flip, mem.dataType)) val wType = BundleType(defaultPortSeq(mem) ++ Seq( |