diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala index e64f6cd9..29200631 100644 --- a/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala +++ b/src/main/scala/firrtl/passes/memlib/ResolveMemoryReference.scala @@ -6,7 +6,6 @@ import firrtl._ import firrtl.ir._ import firrtl.Mappers._ import firrtl.annotations._ -import firrtl.options.PreservesAll import firrtl.stage.Forms /** A component, e.g. register etc. Must be declared only once under the TopAnnotation */ @@ -16,11 +15,12 @@ case class NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnot /** Resolves annotation ref to memories that exactly match (except name) another memory */ -class ResolveMemoryReference extends Transform with DependencyAPIMigration with PreservesAll[Transform] { +class ResolveMemoryReference extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty override def optionalPrerequisiteOf = Forms.MidEmitters + override def invalidates(a: Transform) = false /** Helper class for determining when two memories are equivalent while igoring * irrelevant details like name and info |