diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/MemUtils.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemUtils.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala index bf8b9401..b16a7424 100644 --- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala +++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala @@ -29,11 +29,11 @@ object toBitMask { (mask.tpe, dataType) match { case (mt: VectorType, dt: VectorType) => seqCat((0 until mt.size).reverse map { i => - hiermask(WSubIndex(mask, i, mt.tpe, UNKNOWNGENDER), dt.tpe) + hiermask(WSubIndex(mask, i, mt.tpe, UnknownFlow), dt.tpe) }) case (mt: BundleType, dt: BundleType) => seqCat((mt.fields zip dt.fields) map { case (mf, df) => - hiermask(WSubField(mask, mf.name, mf.tpe, UNKNOWNGENDER), df.tpe) + hiermask(WSubField(mask, mf.name, mf.tpe, UnknownFlow), df.tpe) }) case (UIntType(width), dt: GroundType) if width == IntWidth(BigInt(1)) => seqCat(List.fill(bitWidth(dt).intValue)(mask)) @@ -80,9 +80,9 @@ object MemPortUtils { } def memPortField(s: DefMemory, p: String, f: String): Expression = { - val mem = WRef(s.name, memType(s), MemKind, UNKNOWNGENDER) + val mem = WRef(s.name, memType(s), MemKind, UnknownFlow) val t1 = field_type(mem.tpe, p) val t2 = field_type(t1, f) - WSubField(WSubField(mem, p, t1, UNKNOWNGENDER), f, t2, UNKNOWNGENDER) + WSubField(WSubField(mem, p, t1, UnknownFlow), f, t2, UnknownFlow) } } |