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-rw-r--r--src/main/scala/firrtl/passes/memlib/MemUtils.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemUtils.scala b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
index b16a7424..bb441ebb 100644
--- a/src/main/scala/firrtl/passes/memlib/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemUtils.scala
@@ -79,7 +79,7 @@ object MemPortUtils {
(mem.readwriters map (Field(_, Flip, rwType))))
}
- def memPortField(s: DefMemory, p: String, f: String): Expression = {
+ def memPortField(s: DefMemory, p: String, f: String): WSubField = {
val mem = WRef(s.name, memType(s), MemKind, UnknownFlow)
val t1 = field_type(mem.tpe, p)
val t2 = field_type(t1, f)