1 files changed, 8 insertions, 8 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemTransformUtils.scala b/src/main/scala/firrtl/passes/memlib/MemTransformUtils.scala
index b6a9a23d..f153fa2b 100644
--- a/src/main/scala/firrtl/passes/memlib/MemTransformUtils.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemTransformUtils.scala
@@ -11,12 +11,12 @@ import MemPortUtils.{MemPortMap}
 object MemTransformUtils {
 
   /** Replaces references to old memory port names with new memory port names
-   */
+    */
   def updateStmtRefs(repl: MemPortMap)(s: Statement): Statement = {
     //TODO(izraelevitz): check speed
     def updateRef(e: Expression): Expression = {
-      val ex = e map updateRef
-      repl getOrElse (ex.serialize, ex)
+      val ex = e.map(updateRef)
+      repl.getOrElse(ex.serialize, ex)
     }
 
     def hasEmptyExpr(stmt: Statement): Boolean = {
@@ -24,16 +24,16 @@ object MemTransformUtils {
       def testEmptyExpr(e: Expression): Expression = {
         e match {
           case EmptyExpression => foundEmpty = true
-          case _ =>
+          case _               =>
         }
-        e map testEmptyExpr // map must return; no foreach
+        e.map(testEmptyExpr) // map must return; no foreach
       }
-      stmt map testEmptyExpr
+      stmt.map(testEmptyExpr)
       foundEmpty
     }
 
     def updateStmtRefs(s: Statement): Statement =
-      s map updateStmtRefs map updateRef match {
+      s.map(updateStmtRefs).map(updateRef) match {
         case c: Connect if hasEmptyExpr(c) => EmptyStmt
         case s => s
       }
@@ -42,6 +42,6 @@ object MemTransformUtils {
   }
 
   def defaultPortSeq(mem: DefAnnotatedMemory): Seq[Field] = MemPortUtils.defaultPortSeq(mem.toMem)
-  def memPortField(s: DefAnnotatedMemory, p: String, f: String): WSubField =
+  def memPortField(s:     DefAnnotatedMemory, p: String, f: String): WSubField =
     MemPortUtils.memPortField(s.toMem, p, f)
 }