1 files changed, 47 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemTransformUtils.scala b/src/main/scala/firrtl/passes/memlib/MemTransformUtils.scala
new file mode 100644
index 00000000..78a386b2
--- /dev/null
+++ b/src/main/scala/firrtl/passes/memlib/MemTransformUtils.scala
@@ -0,0 +1,47 @@
+package firrtl.passes
+package memlib
+
+import firrtl._
+import firrtl.ir._
+import firrtl.Utils._
+import firrtl.Mappers._
+import AnalysisUtils._
+import MemPortUtils.{MemPortMap}
+
+object MemTransformUtils {
+
+  /** Replaces references to old memory port names with new memory port names
+   */
+  def updateStmtRefs(repl: MemPortMap)(s: Statement): Statement = {
+    //TODO(izraelevitz): check speed
+    def updateRef(e: Expression): Expression = {
+      val ex = e map updateRef
+      repl getOrElse (ex.serialize, ex)
+    }
+
+    def hasEmptyExpr(stmt: Statement): Boolean = {
+      var foundEmpty = false
+      def testEmptyExpr(e: Expression): Expression = {
+        e match {
+          case EmptyExpression => foundEmpty = true
+          case _ =>
+        }
+        e map testEmptyExpr // map must return; no foreach
+      }
+      stmt map testEmptyExpr
+      foundEmpty
+    }
+
+    def updateStmtRefs(s: Statement): Statement =
+      s map updateStmtRefs map updateRef match {
+        case c: Connect if hasEmptyExpr(c) => EmptyStmt
+        case s => s
+      }
+
+    updateStmtRefs(s)
+  }
+
+  def defaultPortSeq(mem: DefAnnotatedMemory): Seq[Field] = MemPortUtils.defaultPortSeq(mem.toMem)
+  def memPortField(s: DefAnnotatedMemory, p: String, f: String): Expression =
+    MemPortUtils.memPortField(s.toMem, p, f)
+}