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-rw-r--r--src/main/scala/firrtl/passes/memlib/MemIR.scala19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemIR.scala b/src/main/scala/firrtl/passes/memlib/MemIR.scala
index a7ef9d43..55f0f571 100644
--- a/src/main/scala/firrtl/passes/memlib/MemIR.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemIR.scala
@@ -7,6 +7,25 @@ import firrtl._
import firrtl.ir._
import Utils.indent
+object DefAnnotatedMemory {
+ def apply(m: DefMemory): DefAnnotatedMemory = {
+ new DefAnnotatedMemory(
+ m.info,
+ m.name,
+ m.dataType,
+ m.depth,
+ m.writeLatency,
+ m.readLatency,
+ m.readers,
+ m.writers,
+ m.readwriters,
+ m.readUnderWrite,
+ None, // mask granularity annotation
+ None // No reference yet to another memory
+ )
+ }
+}
+
case class DefAnnotatedMemory(
info: Info,
name: String,