diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/MemConf.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/MemConf.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemConf.scala b/src/main/scala/firrtl/passes/memlib/MemConf.scala index e53a5de7..18fcbf37 100644 --- a/src/main/scala/firrtl/passes/memlib/MemConf.scala +++ b/src/main/scala/firrtl/passes/memlib/MemConf.scala @@ -29,7 +29,7 @@ object MemPort { case class MemConf( name: String, - depth: Int, + depth: BigInt, width: Int, ports: Map[MemPort, Int], maskGranularity: Option[Int] @@ -57,7 +57,7 @@ object MemConf { }).flatten } - def apply(name: String, depth: Int, width: Int, readPorts: Int, writePorts: Int, readWritePorts: Int, maskGranularity: Option[Int]): MemConf = { + def apply(name: String, depth: BigInt, width: Int, readPorts: Int, writePorts: Int, readWritePorts: Int, maskGranularity: Option[Int]): MemConf = { val ports: Map[MemPort, Int] = (if (maskGranularity.isEmpty) { (if (writePorts == 0) Map.empty[MemPort, Int] else Map(WritePort -> writePorts)) ++ (if (readWritePorts == 0) Map.empty[MemPort, Int] else Map(ReadWritePort -> readWritePorts)) |