1 files changed, 41 insertions, 24 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemConf.scala b/src/main/scala/firrtl/passes/memlib/MemConf.scala
index 3809c47c..871a1093 100644
--- a/src/main/scala/firrtl/passes/memlib/MemConf.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemConf.scala
@@ -3,7 +3,6 @@
 package firrtl.passes
 package memlib
 
-
 sealed abstract class MemPort(val name: String) { override def toString = name }
 
 case object ReadPort extends MemPort("read")
@@ -19,22 +18,27 @@ object MemPort {
   def apply(s: String): Option[MemPort] = MemPort.all.find(_.name == s)
 
   def fromString(s: String): Map[MemPort, Int] = {
-    s.split(",").toSeq.map(MemPort.apply).map(_ match {
-      case Some(x) => x
-      case _ => throw new Exception(s"Error parsing MemPort string : ${s}")
-    }).groupBy(identity).mapValues(_.size).toMap
+    s.split(",")
+      .toSeq
+      .map(MemPort.apply)
+      .map(_ match {
+        case Some(x) => x
+        case _       => throw new Exception(s"Error parsing MemPort string : ${s}")
+      })
+      .groupBy(identity)
+      .mapValues(_.size)
+      .toMap
   }
 }
 
 case class MemConf(
-  name: String,
-  depth: BigInt,
-  width: Int,
-  ports: Map[MemPort, Int],
-  maskGranularity: Option[Int]
-) {
+  name:            String,
+  depth:           BigInt,
+  width:           Int,
+  ports:           Map[MemPort, Int],
+  maskGranularity: Option[Int]) {
 
-  private def portsStr = ports.map { case (port, num) => Seq.fill(num)(port.name).mkString(",") } mkString (",")
+  private def portsStr = ports.map { case (port, num) => Seq.fill(num)(port.name).mkString(",") }.mkString(",")
   private def maskGranStr = maskGranularity.map((p) => s"mask_gran $p").getOrElse("")
 
   // Assert that all of the entries in the port map are greater than zero to make it easier to compare two of these case classes
@@ -49,21 +53,34 @@ object MemConf {
   val regex = raw"\s*name\s+(\w+)\s+depth\s+(\d+)\s+width\s+(\d+)\s+ports\s+([^\s]+)\s+(?:mask_gran\s+(\d+))?\s*".r
 
   def fromString(s: String): Seq[MemConf] = {
-    s.split("\n").toSeq.map(_ match {
-      case MemConf.regex(name, depth, width, ports, maskGran) => Some(MemConf(name, BigInt(depth), width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt)))
-      case "" => None
-      case _ => throw new Exception(s"Error parsing MemConf string : ${s}")
-    }).flatten
+    s.split("\n")
+      .toSeq
+      .map(_ match {
+        case MemConf.regex(name, depth, width, ports, maskGran) =>
+          Some(MemConf(name, BigInt(depth), width.toInt, MemPort.fromString(ports), Option(maskGran).map(_.toInt)))
+        case "" => None
+        case _  => throw new Exception(s"Error parsing MemConf string : ${s}")
+      })
+      .flatten
   }
 
-  def apply(name: String, depth: BigInt, width: Int, readPorts: Int, writePorts: Int, readWritePorts: Int, maskGranularity: Option[Int]): MemConf = {
+  def apply(
+    name:            String,
+    depth:           BigInt,
+    width:           Int,
+    readPorts:       Int,
+    writePorts:      Int,
+    readWritePorts:  Int,
+    maskGranularity: Option[Int]
+  ): MemConf = {
     val ports: Seq[(MemPort, Int)] = (if (maskGranularity.isEmpty) {
-      (if (writePorts == 0) Seq() else Seq(WritePort -> writePorts)) ++
-      (if (readWritePorts == 0) Seq() else Seq(ReadWritePort -> readWritePorts))
-    } else {
-      (if (writePorts == 0) Seq() else Seq(MaskedWritePort -> writePorts)) ++
-      (if (readWritePorts == 0) Seq() else Seq(MaskedReadWritePort -> readWritePorts))
-    }) ++ (if (readPorts == 0) Seq() else Seq(ReadPort -> readPorts))
+                                        (if (writePorts == 0) Seq() else Seq(WritePort -> writePorts)) ++
+                                          (if (readWritePorts == 0) Seq() else Seq(ReadWritePort -> readWritePorts))
+                                      } else {
+                                        (if (writePorts == 0) Seq() else Seq(MaskedWritePort -> writePorts)) ++
+                                          (if (readWritePorts == 0) Seq()
+                                           else Seq(MaskedReadWritePort -> readWritePorts))
+                                      }) ++ (if (readPorts == 0) Seq() else Seq(ReadPort -> readPorts))
     new MemConf(name, depth, width, ports.toMap, maskGranularity)
   }
 }