1 files changed, 7 insertions, 12 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 73fec1ee..661d6df4 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -13,15 +13,7 @@ import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin}
 import WrappedExpression.weq
 import annotations._
 
-object InferReadWriteAnnotation {
-  def apply(t: String) = Annotation(CircuitName(t), classOf[InferReadWrite], "")
-  def apply(target: CircuitName) = Annotation(target, classOf[InferReadWrite], "")
-  def unapply(a: Annotation): Option[(CircuitName)] = a match {
-    case Annotation(CircuitName(t), transform, "") if transform == classOf[InferReadWrite] =>
-      Some(CircuitName(t))
-    case _ => None
-  }
-}
+case object InferReadWriteAnnotation extends NoTargetAnnotation
 
 // This pass examine the enable signals of the read & write ports of memories
 // whose readLatency is greater than 1 (usually SeqMem in Chisel).
@@ -159,10 +151,13 @@ class InferReadWrite extends Transform with SeqTransformBased {
     ResolveKinds,
     ResolveGenders
   )
-  def execute(state: CircuitState): CircuitState = getMyAnnotations(state) match {
-    case Nil => state
-    case Seq(InferReadWriteAnnotation(CircuitName(state.circuit.main))) =>
+  def execute(state: CircuitState): CircuitState = {
+    val runTransform = state.annotations.contains(InferReadWriteAnnotation)
+    if (runTransform) {
       val ret = runTransforms(state)
       CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
+    } else {
+      state
+    }
   }
 }