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-rw-r--r--src/main/scala/firrtl/passes/memlib/InferReadWrite.scala2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index 1663efaa..44f45985 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -85,8 +85,6 @@ object InferReadWritePass extends Pass {
(s: Statement): Statement = s match {
// infer readwrite ports only for non combinational memories
case mem: DefMemory if mem.readLatency > 0 =>
- val ut = UnknownType
- val ug = UNKNOWNGENDER
val readers = new PortSet
val writers = new PortSet
val readwriters = collection.mutable.ArrayBuffer[String]()