diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/memlib/InferReadWrite.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/memlib/InferReadWrite.scala | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala index 3494de45..0602e4f1 100644 --- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala @@ -8,7 +8,7 @@ import firrtl.ir._ import firrtl.Mappers._ import firrtl.PrimOps._ import firrtl.Utils.{one, zero, BoolType} -import firrtl.options.HasScoptOptions +import firrtl.options.{HasShellOptions, ShellOption} import MemPortUtils.memPortField import firrtl.passes.memlib.AnalysisUtils.{Connects, getConnects, getOrigin} import WrappedExpression.weq @@ -147,17 +147,16 @@ object InferReadWritePass extends Pass { // Transform input: Middle Firrtl. Called after "HighFirrtlToMidleFirrtl" // To use this transform, circuit name should be annotated with its TransId. -class InferReadWrite extends Transform with SeqTransformBased with HasScoptOptions { +class InferReadWrite extends Transform with SeqTransformBased with HasShellOptions { def inputForm = MidForm def outputForm = MidForm - def addOptions(parser: OptionParser[AnnotationSeq]): Unit = parser - .opt[Unit]("infer-rw") - .abbr("firw") - .valueName ("<circuit>") - .action( (_, c) => c ++ Seq(InferReadWriteAnnotation, RunFirrtlTransformAnnotation(new InferReadWrite)) ) - .maxOccurs(1) - .text("Enable readwrite port inference for the target circuit") + val options = Seq( + new ShellOption[Unit]( + longOption = "infer-rw", + toAnnotationSeq = (_: Unit) => Seq(InferReadWriteAnnotation, RunFirrtlTransformAnnotation(new InferReadWrite)), + helpText = "Enable read/write port inference for memories", + shortOption = Some("firw") ) ) def transforms = Seq( InferReadWritePass, |