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Diffstat (limited to 'src/main/scala/firrtl/passes/ZeroWidth.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/ZeroWidth.scala | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala index e60d76d1..4f7e2369 100644 --- a/src/main/scala/firrtl/passes/ZeroWidth.scala +++ b/src/main/scala/firrtl/passes/ZeroWidth.scala @@ -8,9 +8,9 @@ import firrtl._ import firrtl.Mappers._ import firrtl.options.Dependency -object ZeroWidth extends Transform { +object ZeroWidth extends Transform with DependencyAPIMigration { - override val prerequisites = + override def prerequisites = Seq( Dependency(PullMuxes), Dependency(ReplaceAccesses), Dependency(ExpandConnects), @@ -24,9 +24,6 @@ object ZeroWidth extends Transform { case _ => false } - def inputForm: CircuitForm = UnknownForm - def outputForm: CircuitForm = UnknownForm - private def makeEmptyMemBundle(name: String): Field = Field(name, Flip, BundleType(Seq( Field("addr", Default, UIntType(IntWidth(0))), |