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-rw-r--r--src/main/scala/firrtl/passes/ZeroWidth.scala16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index e01cfffc..e60d76d1 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -6,8 +6,24 @@ import firrtl.PrimOps._
import firrtl.ir._
import firrtl._
import firrtl.Mappers._
+import firrtl.options.Dependency
object ZeroWidth extends Transform {
+
+ override val prerequisites =
+ Seq( Dependency(PullMuxes),
+ Dependency(ReplaceAccesses),
+ Dependency(ExpandConnects),
+ Dependency(RemoveAccesses),
+ Dependency(Uniquify),
+ Dependency[ExpandWhensAndCheck],
+ Dependency(ConvertFixedToSInt) ) ++ firrtl.stage.Forms.Deduped
+
+ override def invalidates(a: Transform): Boolean = a match {
+ case InferTypes => true
+ case _ => false
+ }
+
def inputForm: CircuitForm = UnknownForm
def outputForm: CircuitForm = UnknownForm