diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogPrep.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogPrep.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogPrep.scala b/src/main/scala/firrtl/passes/VerilogPrep.scala index 6733e9d5..9f5de84e 100644 --- a/src/main/scala/firrtl/passes/VerilogPrep.scala +++ b/src/main/scala/firrtl/passes/VerilogPrep.scala @@ -33,7 +33,7 @@ object VerilogPrep extends Pass with PreservesAll[Transform] { override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty type AttachSourceMap = Map[WrappedExpression, Expression] |