diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogPrep.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogPrep.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogPrep.scala b/src/main/scala/firrtl/passes/VerilogPrep.scala index 2bd17519..358c34e2 100644 --- a/src/main/scala/firrtl/passes/VerilogPrep.scala +++ b/src/main/scala/firrtl/passes/VerilogPrep.scala @@ -32,7 +32,7 @@ object VerilogPrep extends Pass { Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform], Dependency[firrtl.transforms.FlattenRegUpdate], Dependency(passes.VerilogModulusCleanup), - Dependency[firrtl.transforms.VerilogRename] + Dependency[firrtl.transforms.VerilogRename[?]] ) override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized |