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-rw-r--r--src/main/scala/firrtl/passes/VerilogPrep.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogPrep.scala b/src/main/scala/firrtl/passes/VerilogPrep.scala
index 9499889a..2bd17519 100644
--- a/src/main/scala/firrtl/passes/VerilogPrep.scala
+++ b/src/main/scala/firrtl/passes/VerilogPrep.scala
@@ -29,7 +29,7 @@ object VerilogPrep extends Pass {
Dependency[firrtl.transforms.ReplaceTruncatingArithmetic],
Dependency[firrtl.transforms.InlineBitExtractionsTransform],
Dependency[firrtl.transforms.InlineAcrossCastsTransform],
- Dependency[firrtl.transforms.LegalizeClocksTransform],
+ Dependency[firrtl.transforms.LegalizeClocksAndAsyncResetsTransform],
Dependency[firrtl.transforms.FlattenRegUpdate],
Dependency(passes.VerilogModulusCleanup),
Dependency[firrtl.transforms.VerilogRename]