diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogModulusCleanup.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index b4df534f..330ca497 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -24,7 +24,6 @@ import scala.collection.mutable * to emit correct verilog without needing to add temporary nodes */ object VerilogModulusCleanup extends Pass { - def name = "Add temporary nodes with verilog widths for modulus" private def onModule(m: Module): Module = { val namespace = Namespace(m) |