diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogModulusCleanup.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index f063fccf..6debaf93 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -37,7 +37,7 @@ object VerilogModulusCleanup extends Pass with PreservesAll[Transform] { override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override def dependents = Seq.empty + override def optionalPrerequisiteOf = Seq.empty private def onModule(m: Module): Module = { val namespace = Namespace(m) |