diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/VerilogModulusCleanup.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogModulusCleanup.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala index f47ddfbd..f063fccf 100644 --- a/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala +++ b/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala @@ -26,7 +26,7 @@ import scala.collection.mutable */ object VerilogModulusCleanup extends Pass with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ + override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++ Seq( Dependency[firrtl.transforms.BlackBoxSourceHelper], Dependency[firrtl.transforms.FixAddingNegativeLiterals], Dependency[firrtl.transforms.ReplaceTruncatingArithmetic], @@ -35,9 +35,9 @@ object VerilogModulusCleanup extends Pass with PreservesAll[Transform] { Dependency[firrtl.transforms.LegalizeClocksTransform], Dependency[firrtl.transforms.FlattenRegUpdate] ) - override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized - override val dependents = Seq.empty + override def dependents = Seq.empty private def onModule(m: Module): Module = { val namespace = Namespace(m) |