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-rw-r--r--src/main/scala/firrtl/passes/ToWorkingIR.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/ToWorkingIR.scala b/src/main/scala/firrtl/passes/ToWorkingIR.scala
index c271302a..03faaf3c 100644
--- a/src/main/scala/firrtl/passes/ToWorkingIR.scala
+++ b/src/main/scala/firrtl/passes/ToWorkingIR.scala
@@ -6,5 +6,5 @@ import firrtl.Transform
object ToWorkingIR extends Pass {
override def prerequisites = firrtl.stage.Forms.MinimalHighForm
override def invalidates(a: Transform) = false
- def run(c:Circuit): Circuit = c
+ def run(c: Circuit): Circuit = c
}