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Diffstat (limited to 'src/main/scala/firrtl/passes/SplitExpressions.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/SplitExpressions.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala index 43d0ed34..808f9f0d 100644 --- a/src/main/scala/firrtl/passes/SplitExpressions.scala +++ b/src/main/scala/firrtl/passes/SplitExpressions.scala @@ -16,11 +16,11 @@ import scala.collection.mutable // and named intermediate nodes object SplitExpressions extends Pass with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowForm ++ + override def prerequisites = firrtl.stage.Forms.LowForm ++ Seq( Dependency(firrtl.passes.RemoveValidIf), Dependency(firrtl.passes.memlib.VerilogMemDelays) ) - override val dependents = + override def dependents = Seq( Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) |