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Diffstat (limited to 'src/main/scala/firrtl/passes/SplitExpressions.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/SplitExpressions.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala index 808f9f0d..7124111b 100644 --- a/src/main/scala/firrtl/passes/SplitExpressions.scala +++ b/src/main/scala/firrtl/passes/SplitExpressions.scala @@ -20,7 +20,7 @@ object SplitExpressions extends Pass with PreservesAll[Transform] { Seq( Dependency(firrtl.passes.RemoveValidIf), Dependency(firrtl.passes.memlib.VerilogMemDelays) ) - override def dependents = + override def optionalPrerequisiteOf = Seq( Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) |