diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/ReplaceMemMacros.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/ReplaceMemMacros.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala index 33a371a0..2342b193 100644 --- a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala +++ b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala @@ -85,8 +85,8 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass { (s: Statement): Statement = s match { case m: DefMemory if containsInfo(m.info, "useMacro") => if (!containsInfo(m.info, "maskGran")) { - m.writers foreach { w => memPortMap(s"${m.name}.${w}.mask") = EmptyExpression } - m.readwriters foreach { w => memPortMap(s"${m.name}.${w}.wmask") = EmptyExpression } + m.writers foreach { w => memPortMap(s"${m.name}.$w.mask") = EmptyExpression } + m.readwriters foreach { w => memPortMap(s"${m.name}.$w.wmask") = EmptyExpression } } val info = getInfo(m.info, "info") match { case None => NoInfo @@ -118,7 +118,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass { val memMods = new Modules val modules = c.modules map updateMemMods(namespace, memMods) // print conf - writer.serialize + writer.serialize() c copy (modules = modules ++ memMods) } } |