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Diffstat (limited to 'src/main/scala/firrtl/passes/ReplaceMemMacros.scala')
-rw-r--r--src/main/scala/firrtl/passes/ReplaceMemMacros.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
index 7bb9c6c4..0ca1a32f 100644
--- a/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
+++ b/src/main/scala/firrtl/passes/ReplaceMemMacros.scala
@@ -22,7 +22,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
val uniqueMems = mutable.ArrayBuffer[DefMemory]()
def updateMemMods(m: Module) = {
- val memPortMap = mutable.HashMap[String, Expression]()
+ val memPortMap = new MemPortMap
def updateMemStmts(s: Statement): Statement = s match {
case m: DefMemory if containsInfo(m.info, "useMacro") =>
@@ -52,7 +52,7 @@ class ReplaceMemMacros(writer: ConfWriter) extends Pass {
}
val updatedMems = updateMemStmts(m.body)
- val updatedConns = updateStmtRefs(updatedMems, memPortMap.toMap)
+ val updatedConns = updateStmtRefs(memPortMap)(updatedMems)
m.copy(body = updatedConns)
}