aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes/ReplSeqMem.scala
diff options
context:
space:
mode:
Diffstat (limited to 'src/main/scala/firrtl/passes/ReplSeqMem.scala')
-rw-r--r--src/main/scala/firrtl/passes/ReplSeqMem.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/ReplSeqMem.scala b/src/main/scala/firrtl/passes/ReplSeqMem.scala
index 3b51d73f..62546a84 100644
--- a/src/main/scala/firrtl/passes/ReplSeqMem.scala
+++ b/src/main/scala/firrtl/passes/ReplSeqMem.scala
@@ -88,7 +88,7 @@ Optional Arguments:
error("No circuit name specified for ReplSeqMem!" + usage)
)
val target = CircuitName(passCircuit)
- def duplicate(n: Named) = this copy (t = (t replace (s"-c:$passCircuit", s"-c:${n.name}")))
+ def duplicate(n: Named) = this copy (t = t.replace(s"-c:$passCircuit", s"-c:${n.name}"))
}
class ReplSeqMem(transID: TransID) extends Transform with SimpleRun {