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-rw-r--r--src/main/scala/firrtl/passes/ReplSeqMem.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/ReplSeqMem.scala b/src/main/scala/firrtl/passes/ReplSeqMem.scala
index c2c1b303..87b9df11 100644
--- a/src/main/scala/firrtl/passes/ReplSeqMem.scala
+++ b/src/main/scala/firrtl/passes/ReplSeqMem.scala
@@ -44,8 +44,8 @@ class ConfWriter(filename: String) {
// legacy
val maskGran = getInfo(m.info, "maskGran")
val readers = List.fill(m.readers.length)("read")
- val writers = List.fill(m.writers.length)(if (maskGran == None) "write" else "mwrite")
- val readwriters = List.fill(m.readwriters.length)(if (maskGran == None) "rw" else "mrw")
+ val writers = List.fill(m.writers.length)(if (maskGran.isEmpty) "write" else "mwrite")
+ val readwriters = List.fill(m.readwriters.length)(if (maskGran.isEmpty) "rw" else "mrw")
val ports = (writers ++ readers ++ readwriters) mkString ","
val maskGranConf = maskGran match { case None => "" case Some(p) => s"mask_gran $p" }
val width = bitWidth(m.dataType)