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-rw-r--r--src/main/scala/firrtl/passes/RemoveValidIf.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 70a575ad..895cb10f 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -31,7 +31,7 @@ object RemoveValidIf extends Pass {
override def prerequisites = firrtl.stage.Forms.LowForm
- override def dependents =
+ override def optionalPrerequisiteOf =
Seq( Dependency[SystemVerilogEmitter],
Dependency[VerilogEmitter] )