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Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveValidIf.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveValidIf.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala index 06f0874a..68d16c30 100644 --- a/src/main/scala/firrtl/passes/RemoveValidIf.scala +++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala @@ -30,7 +30,7 @@ object RemoveValidIf extends Pass { // Recursive. Replaces IsInvalid with connecting zero private def onStmt(s: Statement): Statement = s map onStmt map onExp match { case invalid @ IsInvalid(info, loc) => loc.tpe match { - case _: AnalogType => invalid // Unclear what we should do, can't remove or we emit invalid Firrtl + case _: AnalogType => EmptyStmt case tpe => Connect(info, loc, getGroundZero(tpe)) } // Register connected to itself (since reset has been made explicit) is a register with no reset |