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Diffstat (limited to 'src/main/scala/firrtl/passes/RemoveCHIRRTL.scala')
-rw-r--r--src/main/scala/firrtl/passes/RemoveCHIRRTL.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index d0498cf0..5e93b3b9 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -99,7 +99,7 @@ object RemoveCHIRRTL extends Transform {
set_enable(rws, "en") ++
set_write(rws, "wdata", "wmask")
val mem = DefMemory(sx.info, sx.name, sx.tpe, sx.size, 1, if (sx.seq) 1 else 0,
- rds map (_.name), wrs map (_.name), rws map (_.name))
+ rds map (_.name), wrs map (_.name), rws map (_.name), sx.readUnderWrite)
Block(mem +: stmts)
case sx: CDefMPort =>
types.get(sx.mem) match {