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Diffstat (limited to 'src/main/scala/firrtl/passes/Passes.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/Passes.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 4a90bd08..61afade6 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -269,7 +269,7 @@ object VerilogWrap extends Pass { } def vWrapS(s: Statement): Statement = { s map vWrapS map vWrapE match { - case sx: Print => sx copy (string = VerilogStringLitHandler.format(sx.string)) + case sx: Print => sx.copy(string = sx.string.verilogFormat) case sx => sx } } |