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-rw-r--r--src/main/scala/firrtl/passes/PadWidths.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 163b2270..22dde436 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -13,15 +13,15 @@ import scala.collection.mutable
// Makes all implicit width extensions and truncations explicit
object PadWidths extends Pass {
- override val prerequisites =
+ override def prerequisites =
((new mutable.LinkedHashSet())
++ firrtl.stage.Forms.LowForm
- Dependency(firrtl.passes.Legalize)
+ Dependency(firrtl.passes.RemoveValidIf)).toSeq
- override val optionalPrerequisites = Seq(Dependency[firrtl.transforms.ConstantPropagation])
+ override def optionalPrerequisites = Seq(Dependency[firrtl.transforms.ConstantPropagation])
- override val dependents =
+ override def dependents =
Seq( Dependency(firrtl.passes.memlib.VerilogMemDelays),
Dependency[SystemVerilogEmitter],
Dependency[VerilogEmitter] )