1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/Legalize.scala b/src/main/scala/firrtl/passes/Legalize.scala
index 7a59605a..8b7b733a 100644
--- a/src/main/scala/firrtl/passes/Legalize.scala
+++ b/src/main/scala/firrtl/passes/Legalize.scala
@@ -3,14 +3,14 @@ package firrtl.passes
 import firrtl.PrimOps._
 import firrtl.Utils.{BoolType, error, zero}
 import firrtl.ir._
-import firrtl.options.{PreservesAll, Dependency}
+import firrtl.options.Dependency
 import firrtl.transforms.ConstantPropagation
 import firrtl.{Transform, bitWidth}
 import firrtl.Mappers._
 
 // Replace shr by amount >= arg width with 0 for UInts and MSB for SInts
 // TODO replace UInt with zero-width wire instead
-object Legalize extends Pass with PreservesAll[Transform] {
+object Legalize extends Pass {
 
   override def prerequisites = firrtl.stage.Forms.MidForm :+ Dependency(LowerTypes)
 
@@ -18,6 +18,8 @@ object Legalize extends Pass with PreservesAll[Transform] {
 
   override def optionalPrerequisiteOf = Seq.empty
 
+  override def invalidates(a: Transform) = false
+
   private def legalizeShiftRight(e: DoPrim): Expression = {
     require(e.op == Shr)
     e.args.head match {