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Diffstat (limited to 'src/main/scala/firrtl/passes/ConvertFixedToSInt.scala')
-rw-r--r--src/main/scala/firrtl/passes/ConvertFixedToSInt.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala b/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
index 8cf0b890..e334b94f 100644
--- a/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
+++ b/src/main/scala/firrtl/passes/ConvertFixedToSInt.scala
@@ -108,7 +108,7 @@ object ConvertFixedToSInt extends Pass {
val newPorts = m.ports.map(p => Port(p.info,p.name,p.direction,toSIntType(p.tpe)))
m match {
case Module(info, name, ports, body) => Module(info,name,newPorts,body)
- case ExtModule(info, name, ports) => ExtModule(info,name,newPorts)
+ case ext: ExtModule => ext.copy(ports = newPorts)
}
}
newModules.foreach(m => moduleTypes(m.name) = module_type(m))