diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala index d54d8088..100b3187 100644 --- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala +++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala @@ -9,14 +9,14 @@ import firrtl.options.{Dependency, PreservesAll} object CommonSubexpressionElimination extends Pass with PreservesAll[Transform] { - override val prerequisites = firrtl.stage.Forms.LowForm ++ + override def prerequisites = firrtl.stage.Forms.LowForm ++ Seq( Dependency(firrtl.passes.RemoveValidIf), Dependency[firrtl.transforms.ConstantPropagation], Dependency(firrtl.passes.memlib.VerilogMemDelays), Dependency(firrtl.passes.SplitExpressions), Dependency[firrtl.transforms.CombineCats] ) - override val dependents = + override def dependents = Seq( Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter] ) |