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-rw-r--r--src/main/scala/firrtl/passes/CheckWidths.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala
index 1be7b34e..6761bc7d 100644
--- a/src/main/scala/firrtl/passes/CheckWidths.scala
+++ b/src/main/scala/firrtl/passes/CheckWidths.scala
@@ -13,9 +13,9 @@ import firrtl.options.{Dependency, PreservesAll}
object CheckWidths extends Pass with PreservesAll[Transform] {
- override val prerequisites = Dependency[passes.InferWidths] +: firrtl.stage.Forms.WorkingIR
+ override def prerequisites = Dependency[passes.InferWidths] +: firrtl.stage.Forms.WorkingIR
- override val dependents = Seq(Dependency[transforms.InferResets])
+ override def dependents = Seq(Dependency[transforms.InferResets])
/** The maximum allowed width for any circuit element */
val MaxWidth = 1000000