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Diffstat (limited to 'src/main/scala/firrtl/passes/CheckWidths.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/CheckWidths.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala index 6761bc7d..3c7ad0a8 100644 --- a/src/main/scala/firrtl/passes/CheckWidths.scala +++ b/src/main/scala/firrtl/passes/CheckWidths.scala @@ -15,7 +15,7 @@ object CheckWidths extends Pass with PreservesAll[Transform] { override def prerequisites = Dependency[passes.InferWidths] +: firrtl.stage.Forms.WorkingIR - override def dependents = Seq(Dependency[transforms.InferResets]) + override def optionalPrerequisiteOf = Seq(Dependency[transforms.InferResets]) /** The maximum allowed width for any circuit element */ val MaxWidth = 1000000 |