diff options
Diffstat (limited to 'src/main/scala/firrtl/passes/CheckWidths.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/CheckWidths.scala | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/CheckWidths.scala b/src/main/scala/firrtl/passes/CheckWidths.scala index 4f1930c1..382490e7 100644 --- a/src/main/scala/firrtl/passes/CheckWidths.scala +++ b/src/main/scala/firrtl/passes/CheckWidths.scala @@ -9,14 +9,16 @@ import firrtl.traversals.Foreachers._ import firrtl.Utils._ import firrtl.constraint.IsKnown import firrtl.annotations.{CircuitTarget, ModuleTarget, Target, TargetToken} -import firrtl.options.{Dependency, PreservesAll} +import firrtl.options.Dependency -object CheckWidths extends Pass with PreservesAll[Transform] { +object CheckWidths extends Pass { override def prerequisites = Dependency[passes.InferWidths] +: firrtl.stage.Forms.WorkingIR override def optionalPrerequisiteOf = Seq(Dependency[transforms.InferResets]) + override def invalidates(a: Transform) = false + /** The maximum allowed width for any circuit element */ val MaxWidth = 1000000 val DshlMaxWidth = getUIntWidth(MaxWidth) |