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-rw-r--r--src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
index 8d595f91..b5149953 100644
--- a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
+++ b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
@@ -281,7 +281,7 @@ class AnnotateValidMemConfigs(reader: Option[YamlFileReader]) extends Pass {
case Some(p) => p append m
}
}
- case s => s map updateStmts
+ case sx => sx map updateStmts
}
def run(c: Circuit) = c copy (modules = c.modules map (_ map updateStmts))