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Diffstat (limited to 'src/main/scala/firrtl/ir')
-rw-r--r--src/main/scala/firrtl/ir/IR.scala29
1 files changed, 27 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/ir/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index f5b80ac6..b9b31427 100644
--- a/src/main/scala/firrtl/ir/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -440,6 +440,24 @@ case class Port(
def serialize: String = s"${direction.serialize} $name : ${tpe.serialize}" + info.serialize
}
+/** Parameters for external modules */
+sealed abstract class Param extends FirrtlNode {
+ def name: String
+ def serialize: String = s"parameter $name = "
+}
+/** Integer (of any width) Parameter */
+case class IntParam(name: String, value: BigInt) extends Param {
+ override def serialize: String = super.serialize + value
+}
+/** IEEE Double Precision Parameter (for Verilog real) */
+case class DoubleParam(name: String, value: Double) extends Param {
+ override def serialize: String = super.serialize + value
+}
+/** String Parameter */
+case class StringParam(name: String, value: StringLit) extends Param {
+ override def serialize: String = super.serialize + value.serialize
+}
+
/** Base class for modules */
abstract class DefModule extends FirrtlNode with IsDeclaration {
val info : Info
@@ -464,9 +482,16 @@ case class Module(info: Info, name: String, ports: Seq[Port], body: Statement) e
/** External Module
*
* Generally used for Verilog black boxes
+ * @param defname Defined name of the external module (ie. the name Firrtl will emit)
*/
-case class ExtModule(info: Info, name: String, ports: Seq[Port]) extends DefModule {
- def serialize: String = serializeHeader("extmodule")
+case class ExtModule(
+ info: Info,
+ name: String,
+ ports: Seq[Port],
+ defname: String,
+ params: Seq[Param]) extends DefModule {
+ def serialize: String = serializeHeader("extmodule") +
+ indent(s"\ndefname = $defname\n" + params.map(_.serialize).mkString("\n"))
def mapStmt(f: Statement => Statement): DefModule = this
def mapPort(f: Port => Port): DefModule = this.copy(ports = ports map f)
def mapString(f: String => String): DefModule = this.copy(name = f(name))