diff options
Diffstat (limited to 'src/main/scala/firrtl/ir/Serializer.scala')
| -rw-r--r-- | src/main/scala/firrtl/ir/Serializer.scala | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/main/scala/firrtl/ir/Serializer.scala b/src/main/scala/firrtl/ir/Serializer.scala index cf919b37..a2864d33 100644 --- a/src/main/scala/firrtl/ir/Serializer.scala +++ b/src/main/scala/firrtl/ir/Serializer.scala @@ -3,7 +3,6 @@ package firrtl.ir import firrtl.Utils -import firrtl.backends.experimental.smt.random.DefRandom import firrtl.constraint.Constraint case class Version(major: Int, minor: Int, patch: Int) { @@ -190,7 +189,7 @@ object Serializer { // We could initialze the StringBuilder size, but this is bad for small modules which may not // even reach the bufferSize. - private implicit val b = new StringBuilder + private implicit val b: StringBuilder = new StringBuilder // The flattening of Whens into WhenBegin and friends requires us to keep track of the // indention level @@ -264,11 +263,6 @@ object Serializer { case DefRegister(info, name, tpe, clock, reset, init) => b ++= "reg "; b ++= name; b ++= " : "; s(tpe); b ++= ", "; s(clock); b ++= " with :"; newLineAndIndent(1) b ++= "reset => ("; s(reset); b ++= ", "; s(init); b += ')'; s(info) - case DefRandom(info, name, tpe, clock, en) => - b ++= "rand "; b ++= name; b ++= " : "; s(tpe); - if (clock.isDefined) { b ++= ", "; s(clock.get); } - en match { case Utils.True() => case _ => b ++= " when "; s(en) } - s(info) case DefInstance(info, name, module, _) => b ++= "inst "; b ++= name; b ++= " of "; b ++= module; s(info) case DefMemory( info, |