aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/checks/CheckResets.scala
diff options
context:
space:
mode:
Diffstat (limited to 'src/main/scala/firrtl/checks/CheckResets.scala')
-rw-r--r--src/main/scala/firrtl/checks/CheckResets.scala13
1 files changed, 11 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/checks/CheckResets.scala b/src/main/scala/firrtl/checks/CheckResets.scala
index d6337f9e..406b7f62 100644
--- a/src/main/scala/firrtl/checks/CheckResets.scala
+++ b/src/main/scala/firrtl/checks/CheckResets.scala
@@ -3,6 +3,7 @@
package firrtl.checks
import firrtl._
+import firrtl.options.{Dependency, PreservesAll}
import firrtl.passes.{Errors, PassException}
import firrtl.ir._
import firrtl.traversals.Foreachers._
@@ -25,10 +26,19 @@ object CheckResets {
// Must run after ExpandWhens
// Requires
// - static single connections of ground types
-class CheckResets extends Transform {
+class CheckResets extends Transform with PreservesAll[Transform] {
def inputForm: CircuitForm = MidForm
def outputForm: CircuitForm = MidForm
+ override val prerequisites =
+ Seq( Dependency(passes.LowerTypes),
+ Dependency(passes.Legalize),
+ Dependency(firrtl.transforms.RemoveReset) ) ++ firrtl.stage.Forms.MidForm
+
+ override val optionalPrerequisites = Seq(Dependency[firrtl.transforms.CheckCombLoops])
+
+ override val dependents = Seq.empty
+
import CheckResets._
private def onStmt(regCheck: RegCheckList, drivers: DirectDriverMap)(stmt: Statement): Unit = {
@@ -72,4 +82,3 @@ class CheckResets extends Transform {
state
}
}
-